ShiboSoftwareDev/solar-battery-charger-module

TSCIRCUIT_ISSUES.md

# tscircuit issues exposed by this board

Primary release testing used `tscircuit@0.0.2225`, `@tscircuit/copper-pour-solver@0.0.42`, and `@tscircuit/checks@0.0.151`. Selected routing behavior was also reproduced with tscircuit 0.0.2354. Updated 2026-08-18.

## 1. Polygon SMT pads are omitted from copper-pour obstacles

Severity: fabrication correctness.

`convertCircuitJsonToInputProblem` handles ordinary SMT-pad shapes but omitted `shape: "polygon"`, even though the downstream solver supports polygon input pads. On this board that allowed the GND pour to cross the Si7288DP's real polygon power pads.

The pinned Bun patch converts polygon pads with their pad id, layer, connectivity key, and point list. A regression should place unrelated and same-net polygon pads inside a pour and verify clearance and connection respectively.

## 2. Polygon SMT-pad obstacles receive zero clearance

Severity: fabrication correctness.

`processObstaclesForPour` used zero margin for non-hole polygons instead of `padMargin`. Adding polygon conversion alone could therefore leave a pour touching a different-net pad boundary. The project patch uses `padMargin` for copper pads and retains `cutoutMargin` for holes/cutouts.

Patch: `patches/@tscircuit%2Fcopper-pour-solver@0.0.42.patch`.

## 3. Concave polygon pads explode default-router obstacle count

Severity: autorouter performance.

An early edge-contact implementation used one concave polygon per layer/contact. SimpleRouteJson decomposed each contact into 114 rectangular obstacles. The 16 top/bottom pads created 1,824 obstacles by themselves; Solver7 then spent more than two million iterations in power-trace expansion without finishing.

The reference footprint constructs each contact from three simple copper rectangles around the semicircular edge opening. Expressing the same copper that way reduced the routing problem to a tractable size. Polygon obstacle decomposition/coalescing needs a regression case.

## 4. PowerTraceExpanderSolver can exhaust iterations on a routable board

Severity: autorouter robustness.

Both 0.0.2225 and 0.0.2354 reached `PowerTraceExpanderSolver ran out of iterations` on legal intermediate placements. Small component moves could make the same default-router problem complete. The later package increased default capacity (about 0.744 to 0.815 in the observed runs) but did not eliminate the failure.

## 5. A failed route or fabrication DRC can still exit code 0

Severity: CI correctness.

Intermediate builds printed solver failure or `Build completed with errors` while the CLI exited successfully. CI must inspect Circuit JSON error records and run independent netlist/connectivity/short checks. Solver or fabrication DRC failure should make `tsci build` nonzero.

## 6. Requested clearance is not a reliable lower bound

Severity: fabrication correctness/usability.

Intermediate routes produced local gaps around 0.10–0.12 mm even when `autorouter.traceClearance` was set to 0.15 or 0.16 mm. Changing the clearance also did not reliably invalidate the route cache. The release intentionally targets the observed 0.10 mm result and JLCPCB's 1 oz process, but the router should honor the configured lower bound and include it in cache identity.

## 7. Tiny placement changes cause large route changes

Severity: determinism/usability.

Sub-millimeter moves caused global topology and via-count changes. Explicit `tracehint` elements were emitted but did not materially steer the default route in the tested cases. Stable incremental routing and effective hint diagnostics would make fabrication iteration much safer.

## 8. Same-net MST branches can create overlapping vias

Severity: routing correctness/usability.

Two intermediate default routes created distinct same-net vias only 0.006–0.03 mm apart while converging on one pad, then emitted `pcb_via_clearance_error`. The final placement avoids the trigger, but the router should merge coincident same-net vias or represent them as one conductive feature.

## 9. Pad-entry route metadata can report impossible subminimum widths

Severity: output semantics/auditing.

The final JSON contains six route-point widths below 0.10 mm. Geometry inspection shows all six are inside endpoint copper pads; one 0.047 mm record spans about 1.01 mm inside the Si7288DP polygon pad. Gerber copper is not exposed at that width. Circuit JSON should explicitly identify pad-internal segments, or downstream width audits must be geometry aware. `scripts/audit-circuit.mts` now checks actual endpoint-pad containment instead of accepting an arbitrary distance threshold.

## 10. DNP does not survive reliably into assembly exports

Severity: fabrication-output correctness.

`J_CTRL` and `J_IO` are `doNotPlace` PCB copper features. The source flag is absent from their generated source-component records, and generic BOM/PnP export includes them. The release generates curated BOM/PnP files that select only components carrying a real JLCPCB/LCSC code. Exporters should preserve `do_not_place` and omit such components by default.

## 11. Prebuilt-JSON relative export paths resolve under the input directory

Severity: CLI usability.

With `dist/index/circuit.json` as input, a relative `-o fabrication/file.zip` is resolved beneath the input directory instead of the current working directory. Absolute output paths work correctly and are used for the release. Relative paths should have documented, consistent semantics.

## 12. PCB-mode short checking stalls while Gerber mode completes

Severity: performance.

`check shorts --mode pcb` stalled in the rasterizer on this outline/pour combination. Gerber mode at 50 px/mm completes and reports no shorts. This project is a useful rasterizer performance fixture.

## 13. Host and project CLIs can expose different check commands

Severity: CLI usability.

An older host `tsci` reported `unknown command 'shorts'`, while project-local 0.0.2225 supports it. `bunx tsci check shorts ...` is the reproducible command. The host error should recommend the local CLI or an upgrade.

## 14. Generated trace arrays trigger a React special-prop warning

Severity: diagnostics.

Keyed generated `<trace>` elements print `key is not a prop`, even though stable keys are required for the list. Removing keys produces React's ordinary missing-key warning. The core should not attempt to read React's special `key` prop.

## 15. Optional 3D model fetches fail noisily

Severity: diagnostics/usability.

Preview/KiCad generation logs a failure for each unavailable remote STEP model. These failures do not affect copper or manufacturing files, but the CLI should summarize optional-model failures separately from build correctness.