astra-abse/t113-s3

Allwinner T113-S3 / JLCPCB C5197687: native saved fanout, LCD top, storage right, 127 perimeter exits, 30 decoupling capacitors, connected GND planes; clean DRC and shorts, all 29 vias connected.

Version
1.2.0
License
MIT
Stars
0

src/decoupling-layout.json

[
	{
		"name": "C_D20",
		"pin": 20,
		"value": "100nF",
		"net": "VCC_PLL",
		"x": 9.8,
		"y": -3.6,
		"rotation": 0
	},
	{
		"name": "C_D26",
		"pin": 26,
		"value": "100nF",
		"net": "VCC_RTC",
		"x": 9.8,
		"y": -1.8,
		"rotation": 0
	},
	{
		"name": "C_D28",
		"pin": 28,
		"value": "2.2uF",
		"net": "LDOA_OUT",
		"x": 9.8,
		"y": 0.0,
		"rotation": 0
	},
	{
		"name": "C_D29",
		"pin": 29,
		"value": "2.2uF",
		"net": "LDO_IN",
		"x": 9.8,
		"y": 1.8,
		"rotation": 0
	},
	{
		"name": "C_D30",
		"pin": 30,
		"value": "2.2uF",
		"net": "LDOB_OUT",
		"x": 9.8,
		"y": 3.6,
		"rotation": 0
	},
	{
		"name": "C_D34",
		"pin": 34,
		"value": "100nF",
		"net": "VCC_PE",
		"x": 6.3,
		"y": 9.8,
		"rotation": 90
	},
	{
		"name": "C_D46",
		"pin": 46,
		"value": "100nF",
		"net": "VDD_SYS0",
		"x": 4.5,
		"y": 9.8,
		"rotation": 90
	},
	{
		"name": "C_D48",
		"pin": 48,
		"value": "100nF",
		"net": "VCC_DRAM0",
		"x": 0.9,
		"y": 9.8,
		"rotation": 90
	},
	{
		"name": "C_D49",
		"pin": 49,
		"value": "100nF",
		"net": "VCC_DRAM1",
		"x": -2.7,
		"y": 9.8,
		"rotation": 90
	},
	{
		"name": "C_D50",
		"pin": 50,
		"value": "100nF",
		"net": "VDD18_DRAM",
		"x": -4.5,
		"y": 9.8,
		"rotation": 90
	},
	{
		"name": "C_D51",
		"pin": 51,
		"value": "100nF",
		"net": "VDD_SYS1",
		"x": -6.3,
		"y": 9.8,
		"rotation": 90
	},
	{
		"name": "C_D65",
		"pin": 65,
		"value": "100nF",
		"net": "VCC_LVDS",
		"x": -9.8,
		"y": 7.2,
		"rotation": 180
	},
	{
		"name": "C_D66",
		"pin": 66,
		"value": "100nF",
		"net": "VCC_PD",
		"x": -9.8,
		"y": 5.4,
		"rotation": 180
	},
	{
		"name": "C_D77",
		"pin": 77,
		"value": "100nF",
		"net": "VCC_TVOUT",
		"x": -9.8,
		"y": 3.6,
		"rotation": 180
	},
	{
		"name": "C_D81",
		"pin": 81,
		"value": "100nF",
		"net": "VDD_SYS2",
		"x": -9.8,
		"y": 1.8,
		"rotation": 180
	},
	{
		"name": "C_D83",
		"pin": 83,
		"value": "100nF",
		"net": "VCC_IO",
		"x": -9.8,
		"y": -0.0,
		"rotation": 180
	},
	{
		"name": "C_D89",
		"pin": 89,
		"value": "2.2uF",
		"net": "AVCC",
		"x": -9.8,
		"y": -3.6,
		"rotation": 180
	},
	{
		"name": "C_D90",
		"pin": 90,
		"value": "470nF",
		"net": "VRA2",
		"x": -9.8,
		"y": -5.4,
		"rotation": 180
	},
	{
		"name": "C_D92",
		"pin": 92,
		"value": "470nF",
		"net": "VRA1",
		"x": -9.8,
		"y": -7.2,
		"rotation": 180
	},
	{
		"name": "C_D97",
		"pin": 97,
		"value": "100nF",
		"net": "HPVCC",
		"x": -6.3,
		"y": -9.8,
		"rotation": 270
	},
	{
		"name": "C_D107",
		"pin": 107,
		"value": "100nF",
		"net": "VCC_TVIN",
		"x": -4.5,
		"y": -9.8,
		"rotation": 270
	},
	{
		"name": "C_D110",
		"pin": 110,
		"value": "1uF",
		"net": "TVIN_VRP",
		"x": -2.7,
		"y": -9.8,
		"rotation": 270
	},
	{
		"name": "C_D111",
		"pin": 111,
		"value": "1uF",
		"net": "TVIN_VRN",
		"x": -0.9,
		"y": -9.8,
		"rotation": 270
	},
	{
		"name": "C_D116",
		"pin": 116,
		"value": "100nF",
		"net": "VDD_CORE0",
		"x": 0.9,
		"y": -9.8,
		"rotation": 270
	},
	{
		"name": "C_D117",
		"pin": 117,
		"value": "100nF",
		"net": "VDD_CORE1",
		"x": 4.5,
		"y": -9.8,
		"rotation": 270
	},
	{
		"name": "C_D128",
		"pin": 128,
		"value": "100nF",
		"net": "VCC_PG",
		"x": 6.3,
		"y": -9.8,
		"rotation": 270
	},
	{
		"name": "C_B46",
		"pin": 46,
		"value": "10uF",
		"net": "VDD_SYS0",
		"x": 2.7,
		"y": 9.8,
		"rotation": 90
	},
	{
		"name": "C_B48",
		"pin": 48,
		"value": "10uF",
		"net": "VCC_DRAM0",
		"x": -0.9,
		"y": 9.8,
		"rotation": 90
	},
	{
		"name": "C_B83",
		"pin": 83,
		"value": "10uF",
		"net": "VCC_IO",
		"x": -9.8,
		"y": -1.8,
		"rotation": 180
	},
	{
		"name": "C_B116",
		"pin": 116,
		"value": "10uF",
		"net": "VDD_CORE0",
		"x": 2.7,
		"y": -9.8,
		"rotation": 270
	}
]