ShiboSoftwareDev/am625sip-linux-board

scripts/build-pmic-vsys-cache.tsx

import { mkdirSync, writeFileSync } from "node:fs"
import { Circuit } from "@tscircuit/core"
import type { AnyCircuitElement } from "circuit-json"
import { PmicVsysSubcircuit } from "../subcircuits/pmic-vsys"
import { namespaceCachePcbTraceIds } from "./namespace-cache-pcb-trace-ids"

const CACHE_PATH = "subcircuits/cache/pmic-vsys.circuit.json"
const INTERNAL_TRACE_COUNT = 10

const getErrors = (circuitJson: AnyCircuitElement[]) =>
  circuitJson.filter(
    (element) =>
      element.type.endsWith("_error") || element.type === "pcb_placement_error",
  )

const getCacheJson = (sourceJson: AnyCircuitElement[]) => {
  let cacheJson = sourceJson.filter((element) => {
    const type = element.type
    return (
      (!type.startsWith("schematic_") || type === "schematic_component") &&
      !type.startsWith("cad_") &&
      !type.endsWith("_warning") &&
      type !== "pcb_debug_object" &&
      type !== "source_project_metadata"
    )
  })

  const schematicSourceComponentIds = new Set(
    cacheJson.flatMap((element) =>
      element.type === "schematic_component"
        ? [element.source_component_id]
        : [],
    ),
  )
  const sourcePorts = cacheJson.filter(
    (element) => element.type === "source_port",
  )

  for (const sourceComponent of cacheJson) {
    if (
      sourceComponent.type !== "source_component" ||
      sourceComponent.ftype !== "simple_chip" ||
      schematicSourceComponentIds.has(sourceComponent.source_component_id)
    ) {
      continue
    }

    const portLabels = Object.fromEntries(
      sourcePorts.flatMap((sourcePort) => {
        if (
          sourcePort.type !== "source_port" ||
          sourcePort.source_component_id !==
            sourceComponent.source_component_id ||
          sourcePort.pin_number == null
        ) {
          return []
        }
        return [[`pin${sourcePort.pin_number}`, sourcePort.name]]
      }),
    )
    if (Object.keys(portLabels).length === 0) continue

    cacheJson.push({
      type: "schematic_component",
      schematic_component_id: `schematic_component_cache_${sourceComponent.source_component_id}`,
      source_component_id: sourceComponent.source_component_id,
      center: { x: 0, y: 0 },
      size: { width: 2, height: 2 },
      is_box_with_pins: true,
      pin_spacing: 0.2,
      port_labels: portLabels,
    })
  }

  const routedSourceTraceIds = new Set(
    cacheJson.flatMap((element) =>
      element.type === "pcb_trace" && element.source_trace_id
        ? [element.source_trace_id]
        : [],
    ),
  )
  cacheJson = cacheJson.filter(
    (element) =>
      element.type !== "source_trace" ||
      routedSourceTraceIds.has(element.source_trace_id),
  )

  for (const element of cacheJson) {
    if (element.type === "pcb_component") element.rotation = 0
  }

  return namespaceCachePcbTraceIds(cacheJson, "pmic-vsys")
}

const main = async () => {
  const sourceCircuit = new Circuit()
  sourceCircuit.on("autorouting:start", (event: any) => {
    console.log(
      `source autorouting start: ${event.phaseName ?? "unphased"} (${event.simpleRouteJson.connections.length} connections)`,
    )
  })
  sourceCircuit.on("autorouting:end", (event: any) => {
    console.log(`source autorouting end: ${event.phaseName ?? "unphased"}`)
  })
  sourceCircuit.add(
    <board
      width="60mm"
      height="60mm"
      layers={4}
      defaultTraceWidth="0.08128mm"
      minTraceWidth="0.08128mm"
      minTraceToPadEdgeClearance="0.05mm"
      minPadEdgeToPadEdgeClearance="0.08128mm"
      minViaEdgeToPadEdgeClearance="0.08128mm"
      minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
      minViaHoleDiameter="0.1mm"
      minViaPadDiameter="0.24mm"
      pcbStyle={{ viaHoleDiameter: "0.1mm", viaPadDiameter: "0.24mm" }}
      autorouter="default"
      schematicDisabled
    >
      <PmicVsysSubcircuit />
    </board>,
  )

  await sourceCircuit.renderUntilSettled()
  const sourceJson = sourceCircuit.getCircuitJson()
  const sourceErrors = getErrors(sourceJson)
  const sourceTraceCount = sourceJson.filter(
    (element) => element.type === "pcb_trace",
  ).length
  const cacheJson = getCacheJson(sourceJson)
  writeFileSync(
    "/private/tmp/pmic-vsys-cache-candidate.circuit.json",
    `${JSON.stringify(cacheJson, null, 2)}\n`,
  )

  if (sourceErrors.length > 0 || sourceTraceCount !== INTERNAL_TRACE_COUNT) {
    console.error(
      JSON.stringify(
        {
          error: "PMIC VSYS source-cache validation failed",
          sourceTraceCount,
          sourceErrors,
        },
        null,
        2,
      ),
    )
    process.exitCode = 1
    return
  }

  if (process.argv.includes("--source-only")) {
    mkdirSync("subcircuits/cache", { recursive: true })
    writeFileSync(CACHE_PATH, `${JSON.stringify(cacheJson, null, 2)}\n`)
    console.log(
      JSON.stringify(
        {
          cachePath: CACHE_PATH,
          sourceTraceCount,
          sourceElementCount: sourceJson.length,
          cacheElementCount: cacheJson.length,
          validation: "source-only",
        },
        null,
        2,
      ),
    )
    return
  }

  const parentCircuit = new Circuit()
  let parentAutoroutingConnectionCount = 0
  parentCircuit.on("autorouting:start", (event: any) => {
    parentAutoroutingConnectionCount += event.simpleRouteJson.connections.length
  })
  parentCircuit.add(
    <board
      width="60mm"
      height="60mm"
      layers={4}
      autorouter="default"
      schematicDisabled
      minTraceWidth="0.08128mm"
      minTraceToPadEdgeClearance="0.05mm"
      minPadEdgeToPadEdgeClearance="0.08128mm"
      minViaEdgeToPadEdgeClearance="0.08128mm"
      minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
      minViaHoleDiameter="0.1mm"
      minViaPadDiameter="0.24mm"
    >
      <subcircuit
        name="PMIC_CACHE"
        circuitJson={cacheJson}
        pcbX={0}
        pcbY={0}
      />
    </board>,
  )

  await parentCircuit.renderUntilSettled()
  const parentJson = parentCircuit.getCircuitJson()
  writeFileSync(
    "/private/tmp/pmic-vsys-cache-parent.circuit.json",
    `${JSON.stringify(parentJson, null, 2)}\n`,
  )
  const parentErrors = getErrors(parentJson)
  const parentTraceCount = parentJson.filter(
    (element) => element.type === "pcb_trace",
  ).length
  const importedNames = ["U2", "C3", "C5", "C6", "R1", "R2", "R13", "R14"]
  const missingImportedComponents = importedNames.filter(
    (name) =>
      !parentJson.some(
        (element) => element.type === "source_component" && element.name === name,
      ),
  )

  if (
    parentErrors.length > 0 ||
    parentTraceCount !== INTERNAL_TRACE_COUNT ||
    parentAutoroutingConnectionCount !== 0 ||
    missingImportedComponents.length > 0
  ) {
    console.error(
      JSON.stringify(
        {
          error: "PMIC VSYS imported-cache validation failed",
          parentTraceCount,
          parentAutoroutingConnectionCount,
          missingImportedComponents,
          parentErrors,
        },
        null,
        2,
      ),
    )
    process.exitCode = 1
    return
  }

  mkdirSync("subcircuits/cache", { recursive: true })
  writeFileSync(CACHE_PATH, `${JSON.stringify(cacheJson, null, 2)}\n`)
  console.log(
    JSON.stringify(
      {
        cachePath: CACHE_PATH,
        sourceTraceCount,
        parentTraceCount,
        parentAutoroutingConnectionCount,
        sourceElementCount: sourceJson.length,
        cacheElementCount: cacheJson.length,
      },
      null,
      2,
    ),
  )
}

main().catch((error) => {
  console.error(error)
  process.exitCode = 1
})