0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

Version
1.0.5
License
unset
Stars
0

tests/module.test.tsx

import { test } from 'bun:test'
import assert from 'node:assert/strict'
import { RootCircuit } from '@tscircuit/core'
import AM3352Module, { LAYOUT_PROFILES, am3352TracePaths } from '@tsci/0hmX.am3352'
test('native package imports and connects a named module', async () => {
assert.ok(Object.hasOwn(LAYOUT_PROFILES, 'native'))
for(const profile of Object.keys(LAYOUT_PROFILES)) assert.ok(LAYOUT_PROFILES[profile as keyof typeof LAYOUT_PROFILES].savedPathCount > 0)
assert.equal(am3352TracePaths.length, 313)
assert.throws(() => AM3352Module({layoutProfile: 'other' as any}), /Unknown AM3352 layoutProfile/)
assert.throws(() => AM3352Module({connections: {UNKNOWN_PIN: 'net.DEBUG'}}), /Unknown AM3352/)
assert.throws(() => AM3352Module({name: 'invalid.name'}), /selector-safe/)
const c = new RootCircuit()
c.add(<board width={40} height={34} layers={6} schematicDisabled routingDisabled allowBlindAndBuriedVias={false}
 minPadEdgeToPadEdgeClearance={.0762} minViaEdgeToPadEdgeClearance={.0762} minTraceToPadEdgeClearance={.0762}>
 <AM3352Module name="SOC" layoutProfile="native" connections={{UART0_TXD: '.DEBUG > .pin1'}}/>
 <chip name="DEBUG" pcbX={12} footprint={<footprint><smtpad portHints={['pin1']} shape="rect" width={.5} height={.5} pcbX={0} pcbY={0}/></footprint>}/>
</board>)
await c.renderUntilSettled()
const json=c.getCircuitJson()
assert.deepEqual(json.filter(e=>e.type.endsWith('_error')), [])
const external=json.find(e=>e.type==='source_trace'&&e.name?.startsWith('SOC_')&&e.name.endsWith('_external'))
assert.ok(external?.type==='source_trace')
const componentNames=external.connected_source_port_ids.map(id=>{
 const port=json.find(e=>e.type==='source_port'&&e.source_port_id===id)
 assert.ok(port?.type==='source_port')
 const component=json.find(e=>e.type==='source_component'&&e.source_component_id===port.source_component_id)
 assert.ok(component?.type==='source_component')
 return component.name
})
assert.deepEqual(componentNames.sort(), ['DEBUG','U1'])
console.log('Package import, registered native profile, named module and external UART connection passed')

},60000)