0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

Version
1.0.5
License
unset
Stars
0

tests/ddr-host.test.tsx

import { test, expect } from 'bun:test'
import { Fragment } from 'react'
import { RootCircuit } from '@tscircuit/core'
import { AM3352Module } from '../src/index'
import { getAM3352TracePaths } from '../src/saved-paths'
import { getAM3352PowerPlanes } from '../src/profiles'
import { routeHostSignals } from '../scripts/check-ddr-host-router'

test('single noncoincident host signal keeps every cached CPU path electrically instantiated', async () => {
 const c=new RootCircuit()
 const planes=getAM3352PowerPlanes('ddr_left')
 const exit=getAM3352TracePaths('ddr_left').find(p=>p.connection==='U1.M3')!.route.at(-1)!
 const destination={x:10+Number(exit.x)-7.5,y:Number(exit.y)-2}
 c.add(<board width={70} height={45} layers={10} schematicDisabled allowBlindAndBuriedVias={false}
  minPadEdgeToPadEdgeClearance={.0762} minTraceToPadEdgeClearance={.0762} minViaEdgeToPadEdgeClearance={.0762}
  autorouter={{algorithmFn:input=>routeHostSignals(input,true)}}>
  {[...new Set(planes.map(p=>p.netName))].map(name=><Fragment key={name}><net name={name}/></Fragment>)}
  {planes.map(p=><Fragment key={`${p.netName}:${p.layer}`}><copperpour layer={p.layer} connectsTo={`net.${p.netName}`} clearance={.1016} boardEdgeMargin={.2}/></Fragment>)}
  <AM3352Module name="CPU" layoutProfile="ddr_left" pcbX={10} connections={{DDR_D0:'.DEST > .pin1'}}/>
  <chip name="DEST" pcbX={destination.x} pcbY={destination.y} footprint={<footprint><smtpad portHints={['pin1']} pcbX={0} pcbY={0} shape="rect" width={.5} height={.5} layer="inner2"/></footprint>}/>
 </board>)
 await c.renderUntilSettled()
 const json=c.getCircuitJson()
 expect(json.filter(e=>e.type.endsWith('_error'))).toEqual([])
 const traces=json.filter(e=>e.type==='pcb_trace')
 for(const path of getAM3352TracePaths('ddr_left')) {
  expect(traces.some(t=>t.route.length===path.route.length&&t.route.every((q:any,i)=>{
   const p:any=path.route[i]
   return q.route_type===p.route_type&&Math.hypot(q.x-(Number(p.x)+10),q.y-Number(p.y))<1e-7&&(p.route_type==='wire'?q.layer===p.layer:q.from_layer===p.from_layer&&q.to_layer===p.to_layer)
  }))).toBe(true)
 }
 const external=json.find(e=>e.type==='source_trace'&&e.name==='CPU_M3_external')
 expect(external?.type).toBe('source_trace')
 const host=traces.find(e=>external?.type==='source_trace'&&e.source_trace_id===external.source_trace_id)
 expect(host).toBeDefined()
 expect(host!.route.length).toBeGreaterThanOrEqual(2)
},60000)