0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

Version
1.0.5
License
unset
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src/pin-map.ts

/** TI AM335x SPRS717L (March 2020), section 4.1.2, ZCZ top-view pin maps,
 * pages 15–17: https://www.ti.com/lit/ds/symlink/am3352.pdf
 * AM3352BZCZD80: 324-ball, 15 × 15 mm, 0.8 mm pitch. Numeric pins are
 * row-major A1..A18, B1..B18, etc. A3 is RESERVED/do-not-connect
 * (Table 4-2 note 3); M5/VPP is NC during operation (section 5.1 note 5).
 */
export const AM3352_ROW_NAMES = "ABCDEFGHJKLMNPRTUV".split("")
export const AM3352_BALL_PITCH = 0.8
export const AM3352_BALL_MAP: Readonly<Record<string, string>> = {
  A1: "VSS",
  A2: "VDD_MPU_MON",
  A3: "RESERVED",
  A4: "RTC_XTALOUT",
  A5: "VSS_RTC",
  A6: "RTC_XTALIN",
  A7: "AIN3",
  A8: "AIN6",
  A9: "VREFN",
  A10: "WARMRSTn",
  A11: "TDO",
  A12: "TCK",
  A13: "MCASP0_ACLKX",
  A14: "MCASP0_AHCLKX",
  A15: "XDMA_EVENT_INTR0",
  A16: "SPI0_CS0",
  A17: "SPI0_SCLK",
  A18: "VSS",
  B1: "DDR_A5",
  B2: "DDR_WEn",
  B3: "DDR_BA2",
  B4: "RTC_KALDO_ENn",
  B5: "RTC_PWRONRSTn",
  B6: "AIN0",
  B7: "AIN2",
  B8: "AIN5",
  B9: "VREFP",
  B10: "TRSTn",
  B11: "TDI",
  B12: "MCASP0_ACLKR",
  B13: "MCASP0_FSX",
  B14: "EMU1",
  B15: "PWRONRSTn",
  B16: "SPI0_D1",
  B17: "SPI0_D0",
  B18: "EXTINTn",
  C1: "DDR_A9",
  C2: "DDR_A4",
  C3: "DDR_A3",
  C4: "DDR_BA0",
  C5: "EXT_WAKEUP",
  C6: "PMIC_POWER_EN",
  C7: "AIN1",
  C8: "AIN4",
  C9: "AIN7",
  C10: "CAP_VBB_MPU",
  C11: "TMS",
  C12: "MCASP0_AHCLKR",
  C13: "MCASP0_FSR",
  C14: "EMU0",
  C15: "SPI0_CS1",
  C16: "I2C0_SCL",
  C17: "I2C0_SDA",
  C18: "ECAP0_IN_PWM0_OUT",
  D1: "DDR_CKn",
  D2: "DDR_CK",
  D3: "DDR_A15",
  D4: "DDR_A8",
  D5: "DDR_A6",
  D6: "CAP_VDD_RTC",
  D7: "VDDS_RTC",
  D8: "VDDA_ADC",
  D9: "CAP_VDD_SRAM_CORE",
  D10: "VDDS_SRAM_MPU_BB",
  D11: "CAP_VDD_SRAM_MPU",
  D12: "MCASP0_AXR0",
  D13: "MCASP0_AXR1",
  D14: "XDMA_EVENT_INTR1",
  D15: "UART1_TXD",
  D16: "UART1_RXD",
  D17: "UART1_RTSn",
  D18: "UART1_CTSn",
  E1: "DDR_BA1",
  E2: "DDR_A7",
  E3: "DDR_A12",
  E4: "DDR_A2",
  E5: "VDDS_DDR",
  E6: "VDDS",
  E7: "VDDS_PLL_DDR",
  E8: "VSSA_ADC",
  E9: "VDDS_SRAM_CORE_BG",
  E10: "VDDSHV6",
  E11: "VDDSHV6",
  E12: "VDDSHV6",
  E13: "VDDSHV6",
  E14: "VDDS",
  E15: "UART0_RXD",
  E16: "UART0_TXD",
  E17: "UART0_RTSn",
  E18: "UART0_CTSn",
  F1: "DDR_CASn",
  F2: "DDR_A11",
  F3: "DDR_A0",
  F4: "DDR_A10",
  F5: "VDDS_DDR",
  F6: "VDD_CORE",
  F7: "VDD_CORE",
  F8: "VSS",
  F9: "VDDS",
  F10: "VDD_MPU",
  F11: "VDD_MPU",
  F12: "VDD_MPU",
  F13: "VDD_MPU",
  F14: "VDDSHV6",
  F15: "USB1_DRVVBUS",
  F16: "USB0_DRVVBUS",
  F17: "MMC0_DAT3",
  F18: "MMC0_DAT2",
  G1: "DDR_ODT",
  G2: "DDR_RESETn",
  G3: "DDR_CKE",
  G4: "DDR_RASn",
  G5: "VDDS_DDR",
  G6: "VDD_CORE",
  G7: "VDD_CORE",
  G8: "VSS",
  G9: "VSS",
  G10: "VDD_CORE",
  G11: "VSS",
  G12: "VSS",
  G13: "VDD_MPU",
  G14: "VDDSHV6",
  G15: "MMC0_DAT1",
  G16: "MMC0_DAT0",
  G17: "MMC0_CLK",
  G18: "MMC0_CMD",
  H1: "DDR_A1",
  H2: "DDR_CSn0",
  H3: "DDR_A13",
  H4: "DDR_A14",
  H5: "VDDS_DDR",
  H6: "VSS",
  H7: "VSS",
  H8: "VSS",
  H9: "VSS",
  H10: "VSS",
  H11: "VDD_CORE",
  H12: "VSS",
  H13: "VDD_MPU",
  H14: "VDDSHV4",
  H15: "VDDS_PLL_MPU",
  H16: "MII1_COL",
  H17: "MII1_CRS",
  H18: "RMII1_REF_CLK",
  J1: "DDR_D8",
  J2: "DDR_DQM1",
  J3: "DDR_VTP",
  J4: "DDR_VREF",
  J5: "VDDS_DDR",
  J6: "VSS",
  J7: "VSS",
  J8: "VSS",
  J9: "VSS",
  J10: "VSS",
  J11: "VSS",
  J12: "VDD_CORE",
  J13: "VDD_MPU",
  J14: "VDDSHV4",
  J15: "MII1_RX_ER",
  J16: "MII1_TX_EN",
  J17: "MII1_RX_DV",
  J18: "MII1_TXD3",
  K1: "DDR_D9",
  K2: "DDR_D10",
  K3: "DDR_D11",
  K4: "DDR_D12",
  K5: "VDDS_DDR",
  K6: "VDD_CORE",
  K7: "VSS",
  K8: "VDD_CORE",
  K9: "VSS",
  K10: "VSS",
  K11: "VSS",
  K12: "VDD_CORE",
  K13: "VDDS",
  K14: "VDDSHV5",
  K15: "MII1_TXD2",
  K16: "MII1_TXD1",
  K17: "MII1_TXD0",
  K18: "MII1_TX_CLK",
  L1: "DDR_DQS1",
  L2: "DDR_DQSn1",
  L3: "DDR_D13",
  L4: "DDR_D14",
  L5: "VDDS_DDR",
  L6: "VDD_CORE",
  L7: "VDD_CORE",
  L8: "VDD_CORE",
  L9: "VDD_CORE",
  L10: "VSS",
  L11: "VSS",
  L12: "VSS",
  L13: "VSS",
  L14: "VDDSHV5",
  L15: "MII1_RXD1",
  L16: "MII1_RXD2",
  L17: "MII1_RXD3",
  L18: "MII1_RX_CLK",
  M1: "DDR_D15",
  M2: "DDR_DQM0",
  M3: "DDR_D0",
  M4: "DDR_D1",
  M5: "VPP",
  M6: "VSS",
  M7: "VSS",
  M8: "VSS",
  M9: "VSS",
  M10: "VSS",
  M11: "VDD_CORE",
  M12: "VSS",
  M13: "VDD_CORE",
  M14: "VSSA_USB",
  M15: "USB0_CE",
  M16: "MII1_RXD0",
  M17: "MDIO",
  M18: "MDC",
  N1: "DDR_D2",
  N2: "DDR_D3",
  N3: "DDR_D4",
  N4: "DDR_D5",
  N5: "VDDSHV6",
  N6: "VDDS",
  N7: "VSS",
  N8: "VDD_CORE",
  N9: "VDD_CORE",
  N10: "VSS",
  N11: "VSS",
  N12: "VDD_CORE",
  N13: "VDD_CORE",
  N14: "VSSA_USB",
  N15: "VDDA3P3V_USB0",
  N16: "VDDA1P8V_USB0",
  N17: "USB0_DP",
  N18: "USB0_DM",
  P1: "DDR_DQS0",
  P2: "DDR_DQSn0",
  P3: "DDR_D6",
  P4: "DDR_D7",
  P5: "VDDSHV6",
  P6: "VDDSHV6",
  P7: "VDDSHV1",
  P8: "VDDSHV1",
  P9: "VDDS",
  P10: "VDDSHV2",
  P11: "VDDSHV2",
  P12: "VDDSHV3",
  P13: "VDDSHV3",
  P14: "VDDS",
  P15: "USB0_VBUS",
  P16: "USB0_ID",
  P17: "USB1_ID",
  P18: "USB1_CE",
  R1: "LCD_DATA0",
  R2: "LCD_DATA1",
  R3: "LCD_DATA2",
  R4: "LCD_DATA3",
  R5: "LCD_HSYNC",
  R6: "LCD_AC_BIAS_EN",
  R7: "GPMC_ADVn_ALE",
  R8: "GPMC_AD2",
  R9: "GPMC_AD6",
  R10: "VDDS_PLL_CORE_LCD",
  R11: "VDDS_OSC",
  R12: "GPMC_AD13",
  R13: "GPMC_A0",
  R14: "GPMC_A4",
  R15: "VDDA3P3V_USB1",
  R16: "VDDA1P8V_USB1",
  R17: "USB1_DP",
  R18: "USB1_DM",
  T1: "LCD_DATA4",
  T2: "LCD_DATA5",
  T3: "LCD_DATA6",
  T4: "LCD_DATA7",
  T5: "LCD_DATA15",
  T6: "GPMC_BEn0_CLE",
  T7: "GPMC_OEn_REn",
  T8: "GPMC_AD3",
  T9: "GPMC_AD7",
  T10: "GPMC_AD9",
  T11: "GPMC_AD10",
  T12: "GPMC_AD12",
  T13: "GPMC_CSn3",
  T14: "GPMC_A3",
  T15: "GPMC_A7",
  T16: "GPMC_A10",
  T17: "GPMC_WAIT0",
  T18: "USB1_VBUS",
  U1: "LCD_DATA8",
  U2: "LCD_DATA9",
  U3: "LCD_DATA10",
  U4: "LCD_DATA11",
  U5: "LCD_VSYNC",
  U6: "GPMC_WEn",
  U7: "GPMC_AD0",
  U8: "GPMC_AD4",
  U9: "GPMC_CSn1",
  U10: "GPMC_AD8",
  U11: "XTALOUT",
  U12: "GPMC_AD11",
  U13: "GPMC_AD15",
  U14: "GPMC_A2",
  U15: "GPMC_A6",
  U16: "GPMC_A9",
  U17: "GPMC_WPn",
  U18: "GPMC_BEn1",
  V1: "VSS",
  V2: "LCD_DATA12",
  V3: "LCD_DATA13",
  V4: "LCD_DATA14",
  V5: "LCD_PCLK",
  V6: "GPMC_CSn0",
  V7: "GPMC_AD1",
  V8: "GPMC_AD5",
  V9: "GPMC_CSn2",
  V10: "XTALIN",
  V11: "VSS_OSC",
  V12: "GPMC_CLK",
  V13: "GPMC_AD14",
  V14: "GPMC_A1",
  V15: "GPMC_A5",
  V16: "GPMC_A8",
  V17: "GPMC_A11",
  V18: "VSS",
}
export const AM3352_NC_BALLS = ["A3", "M5"] as const
export const AM3352_PINS = AM3352_ROW_NAMES.flatMap((row, rowIndex) =>
  Array.from({ length: 18 }, (_, columnIndex) => {
    const ballName = `${row}${columnIndex + 1}`
    return {
      pinNumber: rowIndex * 18 + columnIndex + 1,
      ballName,
      name: AM3352_BALL_MAP[ballName]!,
      x: Number(((columnIndex - 8.5) * AM3352_BALL_PITCH).toFixed(3)),
      y: Number(((8.5 - rowIndex) * AM3352_BALL_PITCH).toFixed(3)),
    }
  }),
)
export function getAm3352Pin(pinNumber: number) {
  const pin = AM3352_PINS[pinNumber - 1]
  if (!pin) throw new Error(`Unknown AM3352 pin ${pinNumber}`)
  return pin
}