0hmX/am3352
This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.
- Version
- 1.0.5
- License
- unset
- Stars
- 0
scripts/audit-ddr-host-reference-coverage.ts
/** Exact planar projection diagnostic. Coverage is not an impedance/return-current proof. */
import { readFileSync, writeFileSync } from 'node:fs'
import { resolve } from 'node:path'
import { objectHash } from './improve-ddr-a9-power-launches'
type P={x:number;y:number}
const cross=(a:P,b:P)=>a.x*b.y-a.y*b.x
const sub=(a:P,b:P)=>({x:a.x-b.x,y:a.y-b.y})
function inside(p:P,ring:P[]){let yes=false;for(let i=0,j=ring.length-1;i<ring.length;j=i++) {const a=ring[j]!,b=ring[i]!;if((a.y>p.y)!==(b.y>p.y)&&p.x<(b.x-a.x)*(p.y-a.y)/(b.y-a.y)+a.x)yes=!yes}return yes}
export function planeCoverageIntervals(a:P,b:P,brep:any){
const rings:P[][]=[brep?.outer_ring?.vertices,...(brep?.inner_rings??[]).map((h:any)=>h.vertices)]
if(rings.some(r=>!Array.isArray(r)||r.length<3||r.some(p=>!Number.isFinite(p.x)||!Number.isFinite(p.y)))||![a.x,a.y,b.x,b.y].every(Number.isFinite))throw Error('Malformed projection geometry')
const d=sub(b,a),length=Math.hypot(d.x,d.y);if(length<1e-9)return[]
const ts=[0,1]
for(const ring of rings)for(let i=0;i<ring.length;i++){
const p=ring[i]!,q=ring[(i+1)%ring.length]!,e=sub(q,p),pa=sub(p,a),den=cross(d,e)
if(Math.abs(den)<1e-12){if(Math.abs(cross(pa,d))<1e-10)for(const v of[p,q]){const t=((v.x-a.x)*d.x+(v.y-a.y)*d.y)/(length*length);if(t>0&&t<1)ts.push(t)};continue}
const t=cross(pa,e)/den,u=cross(pa,d)/den;if(t>0&&t<1&&u>=-1e-10&&u<=1+1e-10)ts.push(t)
}
const points=[...new Set(ts)].sort((x,y)=>x-y),out:Array<{from:number;to:number;covered:boolean;lengthMm:number}>=[]
const onEdge=(p:P,ring:P[])=>ring.some((q,i)=>{const r=ring[(i+1)%ring.length]!,e=sub(r,q),pq=sub(p,q);return Math.abs(cross(e,pq))<1e-9&&pq.x*e.x+pq.y*e.y>=-1e-9&&pq.x*e.x+pq.y*e.y<=e.x*e.x+e.y*e.y+1e-9})
for(let i=1;i<points.length;i++){const from=points[i-1]!,to=points[i]!;if(to-from<1e-10)continue;const t=(from+to)/2,p={x:a.x+t*d.x,y:a.y+t*d.y};const covered=inside(p,rings[0]!)&&!rings.some(r=>onEdge(p,r))&&!rings.slice(1).some(r=>inside(p,r));out.push({from,to,covered,lengthMm:(to-from)*length})}
return out
}
if(import.meta.main){
const dir=resolve(process.argv[2]??'dist/ddr-facing-progress-45'),read=(name:string)=>JSON.parse(readFileSync(resolve(dir,name),'utf8')),circuit=read('candidate.circuit.json'),host=read('host-bundle.json'),report=read('report.json')
if(report.candidateCircuitSha256!==objectHash(circuit)||host.layerSpace!=='physical'||host.traces.some((t:any)=>objectHash(t)!==objectHash(circuit.find((e:any)=>e.type==='pcb_trace'&&e.pcb_trace_id===t.pcb_trace_id))))throw Error('Candidate/host provenance mismatch')
const layers=['top',...Array.from({length:8},(_,i)=>`inner${i+1}`),'bottom'],planes=circuit.filter((e:any)=>e.type==='pcb_copper_pour'),rows:any[]=[]
for(const trace of host.traces)for(let i=1;i<trace.route.length;i++){
const a=trace.route[i-1],b=trace.route[i];if(a.route_type!=='wire'||b.route_type!=='wire'||a.layer!==b.layer||Math.hypot(b.x-a.x,b.y-a.y)<1e-9)continue
const k=layers.indexOf(a.layer);if(k<0)throw Error('Unknown physical layer')
const adjacent=planes.filter((p:any)=>[layers[k-1],layers[k+1]].includes(p.layer))
if(!adjacent.length)rows.push({traceId:trace.pcb_trace_id,connection:trace.connection_name,index:i,signalLayer:a.layer,a,b,referenceLayer:null,totalMm:Math.hypot(b.x-a.x,b.y-a.y),uncoveredMm:Math.hypot(b.x-a.x,b.y-a.y),reason:'No rendered adjacent reference plane'})
for(const plane of adjacent){const intervals=planeCoverageIntervals(a,b,plane.brep_shape),uncovered=intervals.filter(p=>!p.covered).map(interval=>{const t=(interval.from+interval.to)/2,midpoint={x:a.x+t*(b.x-a.x),y:a.y+t*(b.y-a.y)},holes=plane.brep_shape.inner_rings.flatMap((ring:any,index:number)=>inside(midpoint,ring.vertices)?[{index,containsOwnHostVia:trace.route.some((p:any)=>p.route_type==='via'&&inside(p,ring.vertices)),bounds:{minX:Math.min(...ring.vertices.map((p:P)=>p.x)),maxX:Math.max(...ring.vertices.map((p:P)=>p.x)),minY:Math.min(...ring.vertices.map((p:P)=>p.y)),maxY:Math.max(...ring.vertices.map((p:P)=>p.y))}}]:[]);return{...interval,midpoint,holes,ownHostViaAntipad:holes.length>0&&holes.every((h:any)=>h.containsOwnHostVia)}});rows.push({traceId:trace.pcb_trace_id,connection:trace.connection_name,index:i,signalLayer:a.layer,a,b,referenceLayer:plane.layer,planeId:plane.pcb_copper_pour_id,totalMm:Math.hypot(b.x-a.x,b.y-a.y),uncoveredMm:uncovered.reduce((n,p)=>n+p.lengthMm,0),uncoveredIntervals:uncovered})}
}
const summary=host.traces.map((t:any)=>({connection:t.connection_name,layers:[...new Set(rows.filter(r=>r.traceId===t.pcb_trace_id).map(r=>r.referenceLayer))].map(layer=>{const relevant=rows.filter(r=>r.traceId===t.pcb_trace_id&&r.referenceLayer===layer);return{referenceLayer:layer,projectedMm:relevant.reduce((n,r)=>n+r.totalMm,0),uncoveredMm:relevant.reduce((n,r)=>n+r.uncoveredMm,0)}})}))
const result={candidateCircuitSha256:objectHash(circuit),hostTracesSha256:objectHash(host.traces),scope:'Exact HOST CENTERLINE projection on rendered immediately adjacent planes. Every plane edge/antipad is reported, including expected own-via antipads. No automatic exemptions or electrical pass/fail; excludes saved escapes, trace-width footprint, field spread, dielectric stackup and return-via/capacitor paths. Boundary-coincident centerlines are conservatively uncovered.',summary,rows}
writeFileSync(resolve(dir,'host-reference-coverage.json'),JSON.stringify(result,null,2)+'\n');console.log(JSON.stringify(summary,null,2))
}