0hmX/am3352

docs/support-circuit-audit.md

# AM3352 support-circuit audit

This section records the original six-layer `native` profile. The ten-layer
`ddr_left`, `ddr_top` and `ddr_bottom` profiles retain this capacitor network
but replace the DDR escape geometry and reference-layer assignment. See
[DDR integration](ddr-integration.md) and [exit contracts](signal-exits.md).

The updated native profile contains 82 bottom-side capacitors: 55 beneath the
15 × 15 mm BGA body and 27 within the existing 1 mm perimeter padding. Its
capacitor copper stays inside the 17 × 17 mm fanout boundary. Six copper layers
and 0.20 mm drilled, 0.40 mm pad through vias are retained.

The network covers the processor's named supply groups from SPRS717L Tables
5-13–5-15 and the processor-side DDR3 bypass counts from Tables 7-64–7-65.
There are 19 core/MPU/LDO capacitors, 22 I/O-bank capacitors, 19 analog and
auxiliary supply capacitors, and 22 DDR supply capacitors. Each of the 20 DDR
high-speed bypass capacitors uses a distinct pair of connection vias; three
are placed between the DDR supply column and the central ground cluster.
The coverage report is `src/generated/native.decoupling.json`. The fanout cache
contains 313 paths; five crowded supply drops are explicit fixed top-layer links
in `src/fixed-supply-drops.ts`. All 318 signal/supply balls are checked against
the combined saved and fixed connections.

The values are nominal component values. Part qualification, effective
capacitance under DC bias, and a complete power-distribution analysis are not
included. External DDR memory, reference/termination networks, clock/reset and
power sequencing belong to the host design. Impedance and complete DDR timing
remain unverified at the complete host-board level.

## PCB guidance review — 2026-09-10

The published native profile has geometric routing checks, but has not passed a
complete TI PCB-layout review. The prior datasheet use covered ball mapping,
package geometry, supplies and the implemented capacitor subset. Do not treat
that as verification of the complete breakout.

Review references: [AM335x datasheet SPRS717L](https://www.ti.com/lit/gpn/am3352),
§5.9 and §7.7.2.3.3; and the
[AM335x Hardware Design Guide SPRABU5](https://www.ti.com/lit/an/sprabu5/sprabu5.pdf).

Findings against the original native source and saved paths:

- The DDR3 stackup guidance requires continuous adjacent reference planes and
  no reference-plane cuts in the routing region. The current mixed signal/power
  layers do not establish those conditions. Saved DDR_* routes use inner2
  (17 routes), inner3 (13) and inner4 (12), as well as top-layer segments.
  Inner3/inner4 routing particularly needs reference-plane redesign or proof.
- Version 1.0.1 contained only 19 core, MPU and CAP_* capacitors. The native
  update adds the missing named supply groups; the count/value and electrical
  connectivity checks are in `scripts/check-supply-decoupling.ts`. This does
  not establish a complete power-distribution analysis.
- The 0.1 mm pair-skew check does not verify impedance, return-current paths,
  DDR byte-lane/address timing, keepouts or the complete route to memory.
- Table 7-62 specifies a 4 mil minimum trace width. Native's 3.2 mil
  tracks and 0.40/0.20 mm vias fail the implemented DDR geometry gate. The new
  DDR paths use 4 mil tracks and 0.4572/0.254 mm escape vias; impedance remains
  a separate stackup-dependent check.

The registered `ddr_left`, `ddr_top` and `ddr_bottom` profiles each have
313 saved paths plus the same 173 fixed traces. All 52 DDR-related terminals
reach the selected side. Independent full-copper DRC, stricter DDR-to-all-copper
clearance, local pair checks, rendered reference-plane continuity, supply
contacts, transformations and ten-layer shorts checks pass. Full DDR timing,
class-spacing/coupling and impedance still require a defined host stackup and
complete two-memory implementation. The bounded automatic-routing diagnostic
has not completed; the explicit single-DQ host continuation is separately
verified. These results do not certify a complete DDR3 board.

## Source provenance

These AM3352 pin-map, bus, footprint and breakout helpers are adapted from
https://github.com/tscircuit/dataset-fanout31-am62l at commit
3ee11058ca4abb40aba51ca5dc44c039c368416a, referenced by the examples in
https://github.com/tscircuit/fanout-solver.

Local changes: AM3352BZCZ100 part identity; complete pin labels; courtyard;
82 real backside decouplers; four CAP_* outputs terminate locally at capacitors
instead of external target pads; explicit pinned FanoutSolver integration.
The coordinate convention follows the example: top view, A1 upper left.

The decoupling pattern follows fanout-solver's
scripts/generate-repro/create-am62l-real-decoupling-repro.tsx: real capacitor
pads, via barrels and supplied PCB traces are present before fanout solving.