0hmX/am3352

docs/real-ddr-acceptance.md

# Complete AM3352 + two MT41K512M8 interface acceptance

The breakout is a reusable routing fragment. Passing its bend, clearance and local pair checks does not prove a working memory interface. The supplied RAM package also describes its dielectric/impedance model as a placeholder. Its newer `bus_grouped` profile has a different six-layer assignment from the original four-layer profiles; do not run that profile through a four-layer remapping table.

The intended arrangement is two MT41K512M8DA-107 IT:P x8 parts sharing one chip select, forming a 16-bit, 1 GiB rank. The memory's advertised 1866 MT/s speed is not the AM3352 operating rate. Use a provisional 400 MHz clock / 800 MT/s design target; validate the exact CPU ordering code, memory speed-bin operating table, voltage and controller register settings before accepting it. [Micron part catalog](https://www.micron.com/products/memory/dram-components/ddr3-sdram/part-catalog/part-detail/mt41k512m8da-107-it-p)

`src/ddr-board-rules.ts` evaluates supplied complete-board measurements. `measuredRulesPass` excludes electrical evidence. `acceptanceEvidenceComplete` additionally requires a specific report for every evidence gate. Neither field means the evaluator performed an SI simulation. Synthetic evaluator tests are not board test results.

The evaluator also requires `dqlmMm: [byte0, byte1]`, derived from the longest actual connected data/DM ball-pair Manhattan distance for each byte. TI Figure 7-67 defines these placement-derived references and Table 7-69 places DQLM0/DQLM1 in the nominal-length MAX column. Complete DQ/DM routes must not exceed that byte reference; do not use the 0.635 mm skew budget as an extra absolute-length allowance. Matching every signal to an overlong strobe cannot pass this gate. The current frozen placement measures 28.899838/27.300100 mm, and existing long detours fail it. [TI SPRS717L, Figure 7-67 and Table 7-69](https://www.ti.com/lit/ds/sprs717l/sprs717l.pdf)

The implemented numeric rules come from TI Tables 7-68/69: byte skew 0.635 mm, differential skew 0.127 mm, A1+A2 length 63.5 mm, and separate A3, device-stub and termination-stub budgets. Measure named topology segments, not an arbitrary endpoint polyline. Match each byte independently. Include both breakouts and host routes. Nominal center spacing is 3w within data/address classes and 4w between classes; measure the union of reduced-spacing lengths, limited to 31.75 mm. Controlled impedance, continuous adjacent references and return transitions remain separate evidence gates. [TI SPRS717L, §§7.7.2.3.3–7.7.2.3.6](https://www.ti.com/lit/ds/sprs717l/sprs717l.pdf)

For two memories, use the documented shared address/clock topology and termination. Clock uses parallel termination; address/control uses VTT termination; source-series termination is disallowed. Data/strobe use ODT, without external termination. Provide VREF bypassing, a source/sink VTT supply, ZQ resistors, RESET and verified controller configuration. Each RAM needs at least 12 high-speed capacitors totaling 0.85 µF and two bulk capacitors totaling 20 µF; placement and actual power/ground connections matter. [TI SPRS717L, Tables 7-64/65/68/69](https://www.ti.com/lit/ds/sprs717l/sprs717l.pdf)

The following evidence must be produced from the assembled board:

| Gate | Evidence that closes it |
|---|---|
| Complete connectivity | Copper extraction from all CPU pads to the correct RAM pads, including each via barrel and both address loads; no unwanted branch on data nets |
| Clearance and angles | All copper/pads/through-vias, including support components; no >45° turns, including at module joins |
| Coupling and spacing | Actual paired geometry, controlled pair impedance and reduced-spacing budget across the complete interface |
| Keepout and placement | DDR region isolated from other signals; pin-relative placement checked in the TI interface orientation |
| Reference continuity | GND and DDR supply coverage beneath every route, without plane cuts |
| Reference changes | Real ground stitching or reference bypass paths at transitions, with their loop geometry reviewed |
| Fabrication | Named laminate, layer heights, copper thickness, width/gap impedance calculation and fabrication tolerance |
| Via delay/stubs | Physical drill span, unused barrel length and SI impact; planar length alone is insufficient |
| Termination and support | Connected terminating components and configured ODT, VREF/VTT/ZQ/RESET with validated values |
| Power | Memory and CPU decoupling placement, via sharing, supply capacity and return paths |
| Timing | Full-route lengths, layer/via flight time, RAM timing values and controller PHY configuration; SI/timing evidence at the selected rate |

A single explicitly routed DQ connection proves only that one host connection can use the cache. It cannot close the full connectivity, placement, bus congestion or timing gates. No current breakout-only result is a complete-board acceptance report.

## Current physical power limits

The captured `am3352-byte0` / `am3352-byte1` RAM profiles use the ten-layer host mapping and interior address/clock trunk taps. Their original power audit found 38 supply/ground escapes without a local connection via. The existing pad-to-edge lengths of 1.860–2.760 mm already exceed the 1.524 mm RAM-ball-to-connection-via limit; adding a via at those edges cannot repair this.

A separate candidate places 12 × 100 nF high-speed capacitors and 2 × 22 µF bulk capacitors per RAM. Its placement and local copper pass the checks, but nominal capacitance does not establish effective capacitance or power-plane continuity. The 3.81 mm RAM-terminal-to-capacitor-center limit and 2.54 mm capacitor-pad-to-own-via limit are distinct from the 1.524 mm RAM-ball-to-connection-via limit. Do not apply the latter to the distance from a RAM ball to a separate capacitor via. [TI SPRS717L, Tables 7-64/65](https://www.ti.com/lit/ds/sprs717l/sprs717l.pdf)

Candidate geometry and outstanding power-drop work are recorded in [the system progress report](ddr-system-progress.md). These candidates do not modify or qualify the external RAM package.