0hmX/am3352

docs/ddr-current-status.md

# Current DDR integration

Authoritative board: `dist/ddr-clock-zq-power59-final`.
Candidate object SHA256: `f01b00399dc860da389bb195374e8444153b746a35a0fe1d95108f49b5fa4f06`.

**This is a verified partial integration, not a completed DDR interface.**

- All four public CPU profiles pass horizontal/vertical/45° segment and maximum-45° junction checks.
- The combined board preserves 21 of 50 connected DDR signals and qualifies 59 of 60 RAM power launches. RAM0 E9 remains unresolved.
- Both RAM ZQ pins now connect through individual 240-ohm resistors to verified ground copper. The 1% tolerance is a procurement requirement; no manufacturer resistor part is selected.
- Clock escapes now permit a common northbound trunk with at most 45° branch turns. The clock trunk itself remains unrouted.
- Byte0 DQ0–DQ7 and DM retain the measured 28.423158 mm strobe mean after E7/D7 compensation. Byte1 matching remains incomplete. These are planar lengths, excluding package and via delay.
- Each RAM cache contains 72 paths: byte0 has 8 changed/64 unchanged; byte1 has 9 changed/63 unchanged versus the frozen capture. Both have zero added copper-envelope padding, including trace widths and via radii. This excludes separate board support copper and does not prove a globally minimum board size.
- The smallest measured new clock-plane web is 0.127991 mm under the explicit provisional 0.127 mm web / 0.107 mm pour-clearance assumption. Fabrication approval and electrical signoff remain outstanding.

## Clock exit contract

Coordinates are board coordinates in millimetres. These are interior trunk taps, not package-edge exits. Both RAMs are placed at 180°.

| RAM | Clock | Tap X | Tap Y | Physical layer | Via-to-tap world direction | Memory branch from tap |
| --- | --- | ---: | ---: | --- | --- | --- |
| 0 | P | -13.759946 | -7.940100 | inner6 | SE −45° | NW 135° |
| 0 | N | -13.439946 | -7.140000 | inner6 | SW −135° | NE 45° |
| 1 | P | -13.759946 | 5.059900 | inner6 | SE −45° | NW 135° |
| 1 | N | -13.439946 | 5.860000 | inner6 | SW −135° | NE 45° |

Each clock stub measures 0.905097 mm; trunk columns are 0.32 mm apart. All barrels span ten physical layers. The local-frame tangents reverse by 180°. The source-owned contracts and `trunk-direction-audit.json` are authoritative.

## Reuse and remaining work

`DdrMemoryBoardProfile` is bound to this candidate's complete caches. Board replay additionally requires the 22/24 power-path overrides, global planes, host routes, clock-aware routing input and ZQ/support additions in the candidate. The external RAM project was not modified; its default adapter is not interchangeable with this board-specific cache.

Remaining work: D13 and 28 shared/control signals, RAM0 E9 power launch, shared-bus termination and VREF/VTT implementation, complete byte/clock/address timing, fabrication stackup/impedance/return-path validation, and SI/electrical qualification. A green partial geometric audit does not establish a working memory interface.

Evidence in the authoritative directory includes the current evidence manifest, source provenance, both caches and contracts, current byte budgets, full cache-envelope audit, interface-completeness audit, power/reference audits, and support report. Earlier experiment directories and progress notes are historical evidence; their connection counts and geometry must not be used as the current board.